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Analysis of flip flop design using nanoelectronic single electron transistor
Rajasekara, S1, Sundari, G2.
Single Electron Transistor (SET) is a nanoelectronic device that operates under the
controlled mode of tunnelled individual electrons. In this paper, a comparative analysis was
performed employing SET based D-Flip flop with conventional logic D-flip flop. SET is
eminent nanoscale devices that have low power dissipation, high speed and performance.
The flip flop design was simulated using SIMON simulator and the stability of its operation
was analysed applying the Monte-Carlo method that represented stability with low power
dissipation and matched the functionality of traditional CMOS devices.
Affiliation:
- Sathyabama University, India
- Sathyabama University, India
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Indexation |
Indexed by |
MyJurnal (2021) |
H-Index
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2 |
Immediacy Index
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0.000 |
Rank |
0 |
Indexed by |
Scopus 2020 |
Impact Factor
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CiteScore (1.3) |
Rank |
Q3 (Electrical and Electronic Engineering)) Q4 (Electronic, Optical and Magnetic Materials) |
Additional Information |
SJR (0.298) |
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