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An extensive study on different underlap architectures for improved analog/RF performance of 32 nm DG-MOSFET
Avtar Singh1, Arpan Dasgupta2, Rahul Das3, Atanu Kundu4, Saurabh Chaudhury5.
This paper proposed an underlap double-gate MOSFET (U-DG MOSFET) structure with gate stacking. Better sub-threshold slope and RF performance can be obtained from DG MOSFET with symmetrical/asymmetrical drain-source configuration. Simulation shows better results for its upgraded resilient against short channel effects (SCE). The analog and RF performances at 32 nm technology were estimated. Furthermore, the drive capability (on current) of the device, the intrinsic gain (gmRo), the transconductance (gm), and transconductance generation factor (gm/Id) were also evaluated. By using non-quasi-static approach, high frequency parameters such as intrinsic (Cgs and Cgd), parasitic resistance (Rgs and Rgd), transport delay (τm), the unity gain cut-off frequency (fT), and the maximum frequency of oscillation (fmax) were also calculated. A single stage amplifier was then designed to evaluate the performance of the proposed device.
Affiliation:
- Invertis University, India
- University of California, United States
- Jadavpur University, India
- Heritage Institute of Technology, India
- NIT Silchar, India
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| Indexation |
| Indexed by |
MyJurnal (2021) |
| H-Index
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2 |
| Immediacy Index
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0.000 |
| Rank |
0 |
| Indexed by |
Scopus 2020 |
| Impact Factor
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CiteScore (1.3) |
| Rank |
Q3 (Electrical and Electronic Engineering))
Q4 (Electronic, Optical and Magnetic Materials) |
| Additional Information |
SJR (0.298) |
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